One of the challenges of semiconductor development is the disconnect between when companies start work on a project and when we talk about that work. For example: Right now, AMD has teams working on Zen 5, before Zen 4 has even shipped. By the time Zen 5 is imminent, the people who built it will have moved on to other projects.
Earlier this year, AMD demonstrated its upcoming V-Cache designs. These future desktop CPUs will combine the existing Zen 3 architecture with 64MB of additional L3 cache per chiplet, providing an overall performance improvement of about 15 percent. Analyst Yuzo Fukuzaki with TechInsights examined the existing Ryzen 9 5950X and found evidence the chip was designed for modification in this fashion from the beginning.
Images by Yuzo Fukuzaki
There’s a row of dots in the image above. AMD uses TSVs — Through Silicon Vias — to connect the L3 cache directly to the CPU. That’s where the TSVs will run in future V-Cache CPUs. AMD didn’t respin Zen 3 to add V-Cache; it designed the chip to be augmented in this fashion before Zen 3 ever shipped. This kind of forward-looking design is what helps a semiconductor firm execute a regular cadence. Intel has historically dominated the chip industry partly because it mastered this concept and branded it as Tick-Tock. AMD isn’t copying Intel’s old strategy of node shrinks and new architectural improvements, but the company is clearly thinking multiple steps ahead.
Based on these findings, here’s what Fukuzaki thinks the actual design will look like:
TSV pitch; 17μm
KOZ size; 6.2 x 5.3 μm
TSV counts rough estimation; about 23 thousand!!
TSV process position; Between M10-M11 (15 Metals in total, starting from M0)
He also notes that the total amount of L3 cache on AMD CPUs has been rising much more quickly than on Intel or even IBM CPUs. While IBM’s POWER family fields far more cache than any x86 chip, the amount of total onboard cache has not risen very much in recent years. The Broadwell Quad he refers to are the handful of chips Intel shipped with 128MB of onboard EDRAM. The company moved away from this strategy and returned to saving die space and deploying relatively small L3 caches.
AMD has gone a different route with V-NAND and with projects like Infinity Cache. The company has embraced the idea of adding L3 as a way to boost performance. We’re not sure what the impact on power consumption will be, but the idea of adding L3 to increase performance has a long, proud history, right back to the days of the Gallatin Xeon/Pentium 4 Extreme Edition. Granted, back then, Intel only needed to add 2MB — not 64MB — but the principle is the same.
Adding L3 will only boost applications that take advantage of it in the first place, but any workloads that are currently memory bandwidth-bound on Ryzen should see a performance improvement from the additional cache. We’re quite curious to see the impact on power consumption. CPUs tend to pay a consumption penalty for running above 4.5GHz and it’s entirely possible that Zen 3’s efficiency improves more from adding a large L3 cache than from attempting to crank the clock up past 5GHz.
To return to the timing disconnect we mentioned at the beginning of this story: AMD’s V-Cache may well boost the CPU’s efficiency compared with increasing the clock. But it would be incorrect to claim this was an example of how AMD was working to improve x86 efficiency in response to, say, the Apple M1. AMD clearly had plans for V-Cache before Apple’s chip had even been released.
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